Source: verilator-4.040
Section: electronics
Priority: optional
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Build-Depends: debhelper, flex, bison, libfl-dev, python3, gdb, perl
Standards-Version: 4.5.0
Rules-Requires-Root: no
Homepage: https://www.verilator.org

Package: verilator-4.040
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}, perl, perl-doc
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.
